VerilogEval: Evaluating Large Language Models for Verilog Code Generation Paper • 2309.07544 • Published Sep 14, 2023 • 2
VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification Paper • 2505.20302 • Published May 16, 2025 • 1
Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form Paper • 2506.00005 • Published May 7, 2025
CodeV: Empowering LLMs for Verilog Generation through Multi-Level Summarization Paper • 2407.10424 • Published Jul 15, 2024 • 12
Benchmarking Large Language Models for Automated Verilog RTL Code Generation Paper • 2212.11140 • Published Dec 13, 2022 • 1
ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Paper • 2504.14560 • Published Apr 20, 2025
PyraNet: A Multi-Layered Hierarchical Dataset for Verilog Paper • 2412.06947 • Published Dec 9, 2024 • 1
VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation Paper • 2504.15659 • Published Apr 22, 2025
AIvril: AI-Driven RTL Generation With Verification In-The-Loop Paper • 2409.11411 • Published Sep 3, 2024
ITERTL: An Iterative Framework for Fine-tuning LLMs for RTL Code Generation Paper • 2407.12022 • Published Jun 28, 2024
VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation Paper • 2505.11849 • Published May 17, 2025 • 2
Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback Paper • 2504.15804 • Published Apr 22, 2025